This invention relates generally to the field of hardware multithreaded computer processing and more particularly relates to a method to change the number of threads that a hardware multithreaded computer processor is capable of executing.
A hardware multithreaded computer processor maintains the state of more than one thread in architected hardware processors within the processor core. Several threads may execute in a multithreaded processor by merely changing hardware registers each associated with a unique thread. The processor may change registers on every machine cycle or the processor may switch registers, i.e., switch threads, when the processor is idle because, for instance, it is waiting for data or instructions from a more distant cache or memory.
Recently, the processor""s registers, such as the general and special purpose registers and other multithreading memory arrays, have been specialized for multithreading by eliminating read independence. The multithreaded registers/arrays have storage cells that are still arranged in a matrix but each storage cell has a number of storage elements, each associated with a unique thread of operation. Hardware multithreaded processing has surpassed performance expectations and is becoming the normative paradigm of computer architecture.
There are instances, however, when it is desirable to disable one or more threads in the processor. This can happen when a multithreaded processor is needed to function only as a single-threaded processor. An example of a time when a multithreaded processor need only function as a single-threaded processor is during a processor bring-up test which tests the processor design after manufacturing but before any processors are sold to customers. Another time that single-threaded processing is preferred is when the processor is used with operating systems that are not programmed to use the multithreading capability.
Yet another time when it is preferable to disable one or more threads of a multithreaded processor is when defects occur in the multithreaded registers/arrays resulting in a computer failure. To avoid the failure of a computer after its components have been fabricated and assembled, many manufacturers test their processors and memory components before the computers are sold to customers and eliminate the computer components having errors. One type of failure of a processor may be attributed, inter alia, to AC defects of the general and special purpose registers within the processor core and of the computer""s main random access memory caused by stressing the components under normal usage. A processor""s registers/arrays also may undergo LBIST and ABIST tests which test the capacity of a digital storage device to grab and hold a bit for the required time. At the present time, when a multithreaded processor fails one of these tests, it is discarded.
The failure of a processor, however, may be unique to only one or several threads, leaving other threads capable of performing normally. Thus, while a multithreaded processor may not be able to process multiple threads, it may be able to process fewer or only one thread. The processor still has value which can be retrieved when sold with its reduced capacity but which is lost if the processor is discarded.
There is thus a need in the industry to be able to reduce the number of executable threads in a multithreaded processor while still maintaining the processor""s capable to process in a single-threaded mode or in a reduced-thread mode. There is a further need to salvage processors capable of this reduced thread capacity so that the processor can be sold and utilized with its reduced thread capacity and perform either normal single-threaded processing or multithreaded processing of a reduced number of other thread(s) which don""t have defective storage cells.
There is a further need in the industry of multithreaded computers to detect defects in multithreaded registers and/or memory arrays having multithreaded storage elements before the computer is sold to customers. If only those storage elements in a multithreaded memory or register associated with a failed thread becomes unavailable to the processor, the processor itself would not have to be discarded. Thread processing of the thread associated with the defective storage element can be rerouted to storage elements of properly functioning threads.
These needs and others that will become apparent to one skilled in the art are satisfied by a method to change the thread capacity of a hardware multithreaded computer processing system capable of executing a plurality of threads, the method comprising the steps of performing a test capable of isolating the failure of a register/array uniquely associated with each thread; detecting the failure of at least one register/array and recording the thread with which the failed register/array is uniquely associated; disabling access to all register/arrays associated with the thread having the failed register/array; and maintaining access to all register/arrays uniquely associated with other threads not having a detected failure. The step of performing a test capable of isolating the failure of a register/array uniquely of each thread may further comprise executing coded instructions typical of customer performance requirements under stress to exercise critical sections of the register/array. The test may further comprise a logic built-in self test (LBIST) and/or an array built-in self test (ABIST).
The register/array may comprise a multithreaded register/array having storage cells, each storage cell having one storage element uniquely associated with one thread.
The step of disabling access to all register/arrays associated with the thread having the failed register/array may further comprise blowing a fuse to disconnect the read/write ports to the register/array pertaining to the thread having the failed register/array. In an alternative embodiment, the step of disabling access to all register/arrays associated with the thread with which the at least one failed register/array is uniquely associated may comprise disabling any of a plurality of thread switch control events in a hardware thread switch event control register for the thread. Yet, another embodiment envisions that the step of disabling access to all register/arrays associated with the thread with which the at least one failed register/array is uniquely associated further comprises generating a thread switch instruction by executing microcode instructions.
The invention is also considered a method to change the thread capacity of a hardware multithreaded computer processing system capable of executing a plurality of threads, the method comprising the steps of performing a functional test to isolate the failure of a storage element in a multithreaded register/array, the multithreaded register/array arranged in a matrix of storage cells, each storage cell further comprised of a plurality of storage elements each uniquely corresponding to each of the plurality of threads; detecting the failure of at least one storage element and recording the particular thread with which the at least one failed storage element is uniquely associated; disabling all storage elements uniquely corresponding to the particular thread associated with the at least one failed storage element; and routing data for the particular thread to storage elements uniquely associated with other threads.
The above step of disabling all storage elements associated with the particular thread may further comprise generating a thread switch signal by executing microcode instructions in the multithreaded computer to select others of individual storage elements associated with the other threads.
Alternatively, the above step of disabling all storage elements associated with the particular thread further comprises blowing a fuse. The fuse may be positioned at all read/write ports connected to all storage elements for the particular thread. The fuse may be positioned at a thread switch event control register and disable all or part of the thread switch event control register for the particular thread; or the fuse may be connected to individual bits in the thread switch event control register, the individual bits disabling the particular thread. Yet, the fuse may also be connected to a thread state register pertaining to the particular thread; and more distinctly, the fuse may be further connected to individual bits of the thread state register to mark the particular thread as having an inactive status.
The invention is also considered a multithreaded computer system capable of disabling at least one thread of operation, comprising at least one multithreaded computer processor; at least one thread switch control register for each of a plurality of threads of operation in the multithreaded computer processor; at least one hardware multithreaded memory/register array having multithreaded storage cells in which each storage cell has a storage element uniquely associated with one thread of operation; a main memory connected to the at least one multithreaded computer processor; a bus interface connecting the multithreaded computer processor and the main memory to at least one of the group consisting of: a plurality of data storage devices, one or more external communication networks, one or more input/output devices for providing user input to/from the computer processor. The apparatus further comprises a functional test generator to perform a functional test of at least one thread of operation in the at least one multithreaded computer processor during initial bring-up of the processor; a storage element failure detector which detects the failure of a storage element uniquely associated with the at least one thread of operation undergoing the functional test; and a storage element disabler to disable all the storage elements associated with the at least one thread of operation undergoing the functional test in the multithreaded storage cells.
The invention may further be envisioned as a multithreaded processor, comprising: a means to process a plurality of threads; a means to store the state of each of the plurality of threads in hardware registers in the multithreaded processor; a means to detect if any memory storage elements pertaining to an individual thread are defective; a means to disable access to the defective memory storage elements; a means to maintain access to other memory storage elements that are not defective; and a means to redirect processing and storage of the individual thread pertaining to the defective memory storage element to at least one other thread not having defective memory storage elements.